In the prior art, a semiconductor structure is known in which one or more inputs are capacitively connected to the gate of a MOSFET transistor (Metal Oxide Semiconductor Field Effect Transistor). In the present publication, components thus formed are referred to with the designation v-MOSFET. These components can be connected together to form more complex assemblies. FIG. 1 presents the circuit diagram and a cross-sectional view of a possible implementation.
The basic idea of the v-MOSFET transistor is that the input voltages are summed at the gate of the transistor in accordance with capacitive weighting co-efficients. The voltage summed at the gate is given by the equation.       φ    F    =                    ∑                  i          =          1                n            ⁢                        C          i                ⁢                  V          i                                    ∑                  i          =          1                n            ⁢              C        i            
where is the voltage at the floating gate, Ci is the weighting coefficient (capacitance) of input i and Vi is the voltage at input i. By using different combinations of weighting coefficients and inputs, it is possible to implement many functions, such as electric neurons or A/D and D/A converters.
In the V-MOSFET structures presented, a problem is that there are variations and non-idealities in the semiconductor manufacturing process. In addition to the designed inputs, the capacitive coupling between the gate and the substrate causes distortion of the summing.
In the manufacturing process of semiconductor circuits, certain parameters change from one process run to the next, e.g. when there are variations in the alignment of manufacturing masks or in layer thickness. The properties of complex components, such as transistors, are determined by the combined effect of several parameters. Thus, for instance, the threshold voltage of a transistor may vary by as much as ten per cent. FIG. 2 illustrates simulation of the effects of process variations on the threshold voltage of a transistor. In the design of complex v-MOSFET structures, it would be desirable to be able to increase the number of inputs to provide as many inputs as possible. Process variations can be reduced by developing the process itself or by lowering the tolerances permitted in the process, but this leads to increased manufacturing costs. It would also preclude the use of known advantageous manufacturing processes.
The object of the present invention is to eliminate or at least to significantly reduce the problems described above. A further object of the invention is to disclose a new type of semiconductor structure and a method by which non-idealities due to variations in the IC process as well as internal non-idealities in semiconductors can be minimised by electric means.
The invention concerns a method for minimising non-idealities in a semiconductor structure in which a drain, a source, a floating gate and at least one input are disposed on a substrate, the input being capacitively connected to the floating gate. Said semiconductor structure is preferably a v-MOSFET transistor. According to the invention, a conductive layer insulated from the floating gate and at least partially superimposed on the gate is formed in the semiconductor structure. The conductive layer is connected to a constant potential suitably selected, allowing non-idealities of the semiconductor structure to be minimised.
In a preferred embodiment of the invention, an eliminating grid at least partially covering the floating gate is formed from the conductive layer. In this case, the constant potential can be used to eliminate the parasitic substrate capacitance of the floating gate.
In a preferred embodiment of the invention, a control grid of the same material with the input is formed from the conductive layer. The control grid is capacitively connected to the floating gate, in a manner corresponding to the input connection. The control grid is preferably formed in the same layer with the input.
In a preferred embodiment of the invention, a basin located at least partially under the floating gate is formed from the conductive layer.
In a preferred embodiment of the invention, the conductive layer according to the above-described methods is divided into at least two sections so that the potentials of different sections can be controlled independently of each other. The sections can be controlled digitally. The proportions of the sections can also be distributed with a binary weighting.
Moreover, the invention concerns a semiconductor structure comprising a substrate with a drain, source, floating gate and at least one input disposed on it, the input being capacitively connected to the floating gate. According to the invention, the semiconductor structure comprises a conductive layer insulated from the floating gate and at least partially superimposed on the gate. In addition, the conductive layer is connected to a constant potential.
A semiconductor structure according to the invention comprises an eliminating grid formed from the semiconductor structure and at least partially extending over the floating gate.
A semiconductor structure according to the invention comprises a control grid formed from the conductive layer and made of the same material with the input, said control grid being capacitively connected to the floating gate. The control grid is preferably formed in the same layer with the input.
A semiconductor structure according to the invention comprises a basin formed from the conductive layer and disposed at least partially under the floating gate.
In certain embodiments, the semiconductor structures described above are implemented by dividing the conductive layer into at least two sections, allowing the potentials in different sections to be controlled independently of each other. In a preferred case, different sections are provided with digital control. The proportions of the sections can also be distributed with a binary weighting.
The semiconductor structure of the invention can be applied in various implementations, such as A/D converters, digital logic gates, neural network connections, D/A converters or comparators, in which the offset can be electrically corrected.